3-dimensional (3D) packaging technology Essay

Introduction3-dimensional (3D) box engineering is a method use to stick tabu volumetric packaging solution in products. This technology uses the circus tent, otherwise known as the troika or z-dimension, for achieving heightser(prenominal) levels of integration and act in the products. 3D technology chiefly helps in the space- competent integration of the multi-media functions in the products.The puzzle wind among the consumers is to look out for products, having the uttermost functionality in the sm wholeest and lightest possible share. This demand for to a greater extent functions in the smallest volume, calls for advanceder memory capacity, which in turn demands more complex and efficient architectures. In addition, the new product designs in digital handbook, cell ph mavens, digital cameras, PDAs and medication players, require that these features atomic number 18 desegregated development innovative technical form factors and architectures. send off more Social surgery demonstrateThe 3D packaging in new- do times has been associated with the delivering of the highest level of ti integration and scene of action efficiency at the terminal cost, smallest size and best performance. This has resulted in higher growth and brought in newer applications, for the technology.This growth trend in the 3D technology gage be seen since the year 1995. Prior to this, the more or slight efficient and economic way to yield more functionality to an electronic dodge was to integrate all these functions onto the somebody chips victimisation the system on Chip, SOC. However, this method was becoming costlier and as well less efficient, as the issue of functions to be integrated in a sensation chip further increased. In addition, nigh chips that could be integrated together logically were mechanically incompatible, repayable to the different develop heartys utilize.The fork out day technologies in high density packaging have r separatelyed a genuinely advanced stage. Now a iodin chip system put forward be very efficiently cashier into multiple belongs, so as to provide better performance at tear down manufacturing costs.Over the past few years, betray chawing has emerged as a violenceful packaging option for satisfying challenging IC packaging requirements. It holds by integrate chips upendedly in a single tract. This increases the amount of silicon per unit area, which leads to a smaller package footprint, hence conserving system-board accredited estate. In addition, it enables shorter routing interconnects from chip to chip, speeding the communicate surrounded by them. Heterogeneous twirls rear excessively be luxurious using this technology. in that respect is an superfluous benefit of the simplification of climb up-mount system-board assembly, due to the lesser number of components being set on the board.Vias Due to the increasing number of lapses in a stack, the designers are facing the challenge of meeting the temperature design specification. sensation method to counter this is to provide a thermic itinerary from each individual exceed to a substratum using thermic vias. These thermic vias can be implemented using several methods. ace of the approaches is to have a caloric die that caloricly connects each die to the substrate.The warmheartedness up from each die is conducted rapidly from one end of the board to another, either through and through the die attach or the vias. thermic vias are made of copper runs providing the a course of action of least thermal resistance, and so heat is substitutered through the vias in a rest much greater than the area of the vias. Usually one end of via is link up to the IC and the other end is attached to a heat sink. Thermal vias work very well with flip-chip devices. With no additional space required for the heat conduction, these are considered as a mini-thermal solution. by means of silicon Vias Through sil icon vias, TSVs, are upright structures in surrounded by the chips that are utilize as an interconnection to eliminate the subsisting fit bonds. These allow for the shortest electrical path between two sides of wafers or die, used for 3D die-to-die, die-to-wafer, MEMS wafer level packaging. A TSV, three-D chip stacking process hence provides a means of implementing complex, multi chip systems entirely in silicon. TSVs. By the vertical stacking of the blocks using this technology, the wire length of interconnects can monumentally be trim down.Vias provide both electrical and thermal path. In this paper, the thermal enhancement recognize by the vias is discussed along with trying to check out a way to prohibit heat from the dies. The power use to the dies is between 5-10 watts power. We found that one such method was to use silicon dies.Objective of the try outThe methodology of the present employment result be explained in detail in the next section. The study focuses on the future(a) pointsA study was made on the heat transfer enhancement of the stacked die geometry using Through atomic number 14 vias, TSVs, on the die pad location. diametrical schemes were studied.The use of the TSVs to muffle the uttermost join temperature accumulated at the wafers was studiedThe subscribe placement of vias to optimize thermal management, was doFinally, a study of the thermo-mechanical issues, which occurred when TSVs are used, was made.methodological psychoanalysisThe figure below explains the methodology used for this study. First, the package components including the vias were created using Pro / get up Wildfire. After this the corporeal property was defined and the mingled components were assembled. The entire geometry and the properties were then import to Ansys workbench. Here, the Boundary conditions were defined and implemented. Finally, the end result, which is the thermal enhancement of the die geometry, was evaluated.Modeling methodological analysisAny devices thermal properties can be expressed as a part of an electrical round diagram. If, JA is the thermal resistance between joint, and standard atmosphere given in /W, then mathematically JA can be expressed as bewlow The geometry is created using Pro-e, as mentioned in the anterior section. Here, every element should be salve in the UDF library. This is done, so as to cultivate it possible to retrace various separate for assembly. In this assembly area, the area adjoin is done using the mate option, and the vertical and horizontal lines can be joined using the align option.For the analysis, a model Ball Grid Array, BGA, stacked package has been considered. The package substrate is 99 mm in area and is 0.3 mm thick. A fully populated conjoin oaf matrix with a ball count of 56 and a vend of 0.8 mm is used. The stand off height after reflow is 0.2 mm. The heaviness of the mold complex cap is 1.20 mm with the homogeneous dimensions as the package substrate. The diameter of the thermal vias is 0.20mm and its oppressiveness is 0.86mm. The stacked packages have 16 vias and 9 vias. This paper compares the junction temperature of stacked cut with and without vias.Three different package architectures were modeled, to wit a Stacked with spacers die, b Rotated stack die, b pyramid stack die as shown in figure. Three non-volatile dies measuring 6.44.8 mm, with a heaviness of 0.2 mm, form the spacer die. Die thickness is 0.25mm in rotated die. The fall into place PCB is made of a die measuring 3224 mm, with a thickness of 0.6 mm. In the spacer stack die, dummy die is 5.64.0, with a thickness of 0.08mm.For this paper, solderball geometry is modeled closely approximating the real solderball. In solderball geometry, mid diameter is 0.43mm, and choke and provide diameter is 0.33mm, with a height of 0.33mm. Solderball exceed is 0.8mm. These dimensions are not specific to a particular proposition package. They are based on values found in pre sent market for a typical wrought BGA stack package. The details of the package dimensions and material properties of the components is shown in the below.Simulation and berth Studies piece of music doing the Simulation using the Ansys workbench, the following leap conditions need to be use to all the faces of the modeling and to the PCB. The film coefficient is 10W/m C and the Ambient Temperature is 50C. Also a power of 0.3 W ia employ to each of the three dies. By dividing area 0.3W / 6.54.8 (Die area), we can get a heat menstruate as 9765 W/m.The chief(prenominal) physics behind the technology is providing a smooth and rough-and-ready heat transfer path. Due to the high thermal conduction of the copper i.e. the thermal vias, a proportion of the heat much greater than the surface area of the vias leave be transferred.As mentioned in the section above, for the baseline example, an effective heat transfer coefficient of 10 W/m-C with 50c ambient temperature was applied on the tip sort out of the mold cap, and the top and bottom surfaces of the roofy board. For all the three types of stacks, the result was a junction temperature of 116.2C with no vias. When 9 vias were included, for the resembling heat transfer coefficient, the junction temperature was reduced to 111.7C, results in a throw away-off of around 3.6% of the maximum temperature in each of the architectures. By increasing via count to 16 we got the junction temperature to 110.7C effectively cut the junction temperature by 4.49% of the maximum temperature in each of packaging.The figure below explains the proportionate vector plot of heat feed in ANSYS Workbench, where the heat flow path can be seen, which densely collects at the via location. This heat flux is a negatively charged heat flux which is flowing off from the surface and takes away energy out of the body in the form of heatVias can also provide a means of customizing the heat transfer process for devices with a highly non-uniform power distribution. This is particularly important for high density interconnects where the device has highly non-uniform power map.Test flakes in that respect were 12 slickness studies conducted on the simulation test tool. As mentioned earlier, each case was tested with and without vias, and the corresponding temperature plot was drawn. In each case the maximum and minimal temperatures achieved were also noted. For one of the cases it was found that the particular test case no 11 gave a lesser temperature, in the consort of 60-70 degrees.The following is a description of the 12 test cases theatrical role 1 The set-back case consisted of the Dies showing the temperature plot at the film coefficient of 200W/mC. The power applied to the top die, die with vias and the bottom die was 6watts, 2watts, and 2 watts respectively. The maximum temperature achieved was 316.459 C and the stripped temperature was 269.908 C. Applying same conditions without vias gave the maxi mum temperature as 317.2 C and tokenish temperature as 269.591 C.Case 2 For the second case, the Boundary conditions applied were a film co-efficient of 200W/mc and index number of 2 watts applied equally on all the three dice. The maximum temperature achieved was 216.363 C and the stripped temperature was 169.568 C. Applying same conditions without vias gave the maximum temperature as 217.140 C and stripped temperature as 169.55 C.Case 3 For this case, copper was used as the substrate mask and the film coefficient was cd W/mc. The maximum temperature achieved was 178.739 C and the borderline temperature was 144.488 C. Applying same conditions without vias gave the maximum temperature as 179.426 C and lower limit temperature as 144.463 C. The Observation of the above results showed that the temperature difference with and without Vias was solo 1C.Case 4 For this case, convection was applied on board and top die. The power applied to on top, middle and bottom dies was 4wat ts, 3watts, and 3watts respectively. The maximum temperature achieved was 93.775 C and the marginal temperature was 36.098 C. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 93.911 C and minimum temperature as 36.105 C.Case 5 For this case, the enter co-efficient of 400W/mc on top of the top die and 15W/mc on the Pwb. Also 5watts power was applied to each of the dies. The maximum temperature achieved was 209.345 C and the minimum temperature was 128.857 C. It was seen that the minimum Temperature occurs at the top die where the vias were present. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 210.878 C and minimum temperature as 128.739 C, i.e. a drop of only 1.6 C was observed.Case 6 For this case, germanium die was used, instead of silicon die. The maximum temperature achieved was 223.052 C and the minimum temperature was 118.468 C. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 225.219 C and minimum temperature as 118.286 C, i.e. a drop of 2.6 C in the Junction temperature was observed.Case 7 For this case, the take co-efficient on board was ccc W/mc, the Film co-efficient on top surface was 400W/mc, and 5 watts power applied on both dies. The maximum temperature achieved was 119.575 C and the minimum temperature was 43.411 C. Applying same conditions without vias gave the maximum temperature as 120.076 C and minimum temperature as 43/504 C. The maximum change in Junction temperature, with and without vias was observed.0.5 C.Case 8 In this case, a very high thermal conductive material has been used For the through silicon vias (ie.600 W/mc). The maximum temperature achieved was 119.575 C and the minimum temperature was 43.411 C. Applying same conditions without vias gave the maximum temperature as 95.315 C and minimum temperature as 36.347 C. The maximum temperature between i.e. a drop of 2.6 C in the Junction temperature was observed.0.5 C. Though high conductive vias were used there is no large drop in the maximum temperature in the dice.Case 9 The following case used TSVs with the application of higher power( 7 watts) on the top die than the other(a) two dice i.e.., 2 watts on the die with vias and 1 watt on the bottom Die. The maximum temperature achieved was 97.657 C and the minimum temperature was 39.063 C. Applying same conditions without vias gave the maximum temperature as 97.889 C and minimum temperature as 39.032 C. As seen, the TSVs made a vnegligile difference of 0.5 C.Case 10 In this case, the total power on the dice was 5 watts and the power on the die with vias was 5 watts. The maximum temperature achieved was 61.754 C, which was the least temperature, and the minimum temperature was 29.576 C. Applying same conditions without vias gave the maximum temperature as 61.871 C and minimum temperature as 29.55 C.Case 11 In this case, the substrate and su bstrate mask thickness is drastically reduced to 0.075mm and 0.085mm. The maximum temperature achieved was 93.697 C and the minimum temperature was 36.079 C. Applying same conditions without vias gave the maximum temperature as 93.775 C and minimum temperature as 36.067 C.Case 12 In this case, the simulation was done by applying high power of 6 watts on the top die and 2 watts each on the middle and bottom die. The maximum temperature achieved was 88.320 C and the minimum temperature was 35.481 C. Applying same conditions without vias gave the maximum temperature as 88.512 C and minimum temperature as 35.445 C. inductionIn this paper elaborate study has been done in analyzing the effect of thermal vias on the die and ways to occupy down the junction temperature by reduce count. Thermal enhancement was tested by running the thermal simulation with various test cases, and also with / without thermal vias. The Temperature indite of the entire stacked die geometry was plan in Ansys Workbench.It was found that Thermally Through Silicon vias in this particular package did not give a significant effect on performance because of less area of vias and package construction. The use of silicon die did give a lesser temperature as compared to other materials.Future studies will focus on doing the stress analysis of this package with vias, using techniques like thermal shocks for profiling the thermal properties this package in further detail.